In semiconductor memory devices, data is read from or written to the device using address signals and various other control signals. Such memory devices are used for storage of data and/or program code in personal computer systems, embedded processor-based systems, and the like. As with other types of memory, design efforts continue to strive for smaller and faster ferroelectric memories. For example, smaller memory devices can be manufactured typically on a more cost effective basis, to provide devices having higher storage densities. Toward that end, various scaling techniques have been employed to reduce the feature sizes and feature spacings for devices used in making ferroelectric memories, such as transistors and ferroelectric capacitors. However, architectural considerations may limit the amount of density improvement that can be achieved by process scaling techniques alone. Thus, while scaling may allow smaller feature sizes, such approaches typically employ existing memory device layout configurations and interconnection architectures, and so may provide only incremental reductions in device sizes.
Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, which are well known, wherein 1T1C architectures generally offer have smaller memory cell sizes than 2T2C approaches. However, conventional 1T1C and 2T2C approaches both suffer from architecture related limitations on the amount of density increase possible using scaling techniques alone. FIGS. 1A and 1B illustrate a common 1T1C ferroelectric memory cell configuration, wherein a memory device 2 is illustrated schematically in FIG. 1A comprising four such cells 4, and a top structural view thereof is provided in FIG. 1B. The 1T1C memory cells 4 individually comprise a single ferroelectric (FE) capacitor CFE adapted to store a binary data bit, which is connected in series with a MOS type transistor T providing selective access to the FE capacitor CFE during read, restore, and/or write operations.
The gates of the transistors T1–T4 are connected to corresponding wordlines WL1–WL4, respectively, for controlled selection of or access to the FE capacitors CFE1–CFE4, which in turn are connected between first source/drain terminals of the transistors T1–T4 and corresponding platelines PL1–PL4, respectively. Second source/drain terminals of transistors T1 and T2 are connected together and to a bitline BLA. The wordlines WL1–WL4 and platelines PL1–PL4 are controlled so as to selectively provide read, write, and restore accessibility of individual FE capacitors CFE1–CFE4 via the bitline BLA.
As illustrated in FIG. 1B, the cells 4 are organized in groups of two in order to facilitate connection of active regions 6 with a bitline BLA. However, the interconnection of memory cells 4 in this fashion results in a gap 8 between each adjacent pair of cells 4. The gap 8 and other such active area gaps in the device 2 occupy a significant portion of the total wafer area in the device 2, which cannot be eliminated by scaling down the sizes of devices CFE1–4 or T1–4. From FIG. 1B, therefore, it is seen that the architectural interconnection and configuration of the components T and CFE in the conventional 1T1C organization limits the amount of density improvement that can be achieved by process scaling techniques alone.
A similar situation exists for conventional organizations of 2T2C ferroelectric memory cells (not shown), wherein layout gaps are required between active areas of groups of two memory cells, whereby scaling techniques alone cannot achieve optimal utilization of die area in fabricating FE memory devices. Thus, it will be appreciated that the manner in which the ferroelectric memory cells are connected with word lines, bit lines, and plate lines (e.g., the memory cell or array architecture) impacts the overall size of a ferroelectric memory device. Accordingly, there remains a need for improved ferroelectric memory cell configurations and interconnection architectures by which increased device densities and smaller device sizes may be achieved, alone or in combination with feature size scaling techniques.